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magnachip semiconductor ltd. 8-bit single-chip microcontrollers with embedded flash HMS99C51S hms99c52s hms99c54s hms99c56s hms99c58s user?s manual (ver. 1.01)
version 1.01 published by mcu application team ?2004 magnachip semiconductor ltd. all right reserved. additional information of this manual may be served by magnachip semiconductor offices in korea or distrib- utors and representatives li sted at address directory. magnachip semiconductor reserves the right to make changes to any information here in at any time without notice. the information, diagrams and other data in this ma nual are correct and reliab le; however, magnachip semi- conductor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual. revision history ver 1.01 (sep, 10, 2004) this book the company name, hynix semiconductor inc. changed to magnachip semiconductor ltd. ver 1.0 (dec, 01, 2003) the first released document.
HMS99C51S/52s/54s/56s/58s sep. 2004 ver 1.01 contents device naming structure ....... .............. .............. .............. .............. ............1 HMS99C51S/52s/54s/56s /58s selection guide ......... ............ ........... ..........1 feature ........... ................. .............. .............. .............. .............. .............. ............2 pin configuration ....... .............. .............. .............. .............. .............. ............4 pin definitions and functions .............. .............. .............. .............. ..........8 functional description .......... .............. .............. .............. .............. ..........11 cpu ................ ................ ................ ................. .............. .............. .............. ..........12 special function registers .... .............. .............. .............. .............. ........13 x2 mode ......... ................ ................. .............. .............. .............. .............. ..........19 timer / counter 0 and 1 ......... ................. .............. .............. .............. ..........21 timer 2 ........... ................ ................. .............. .............. .............. .............. ..........22 serial interface (uart) ............... ................. ................ ................. ............23 interrupt system ................. ................ ................. .............. .............. ..........24 power saving modes .... ................ ................. ................ ................. ............26 electrical characteristics .. ................. .............. ............... ........... ........27 oscillator circuit ...... .............. .............. .............. .............. .............. ..........39 flash memory ...... ................. ................ ................ ................. .............. ..........43 in-system programming (isp) .. ................. .............. ............... ........... ........55 isp method for pc (magnachip winisp) ........... .............. .............. ..........66
HMS99C51S/52s/54s/56s/58s sep. 2004 ver 1.01
HMS99C51S/52s/54s/56s/58s sep. 2004 ver 1.01 1 device naming structure HMS99C51S/52s/54s/56s/ 58s selection guide operating voltage (v) rom size (bytes) ram size (bytes) device name operating frequency (mhz) flash 4.5~5.5 4k 8k 16k 24k 32k 256 HMS99C51S hms99c52s hms99c54s hms99c56s hms99c58s 40 xx hms99c5xs package type blank: pl: q: 40pdip 44plcc 44mqfp rom size 4: 6: 16k bytes 24k bytes operating voltage c: 4.5~5.5v magnachip semiconductor mcu flash version 8: 32k bytes 1: 4k bytes 2: 8k bytes
HMS99C51S/52s/54s/56s/58s 2 sep. 2004 ver 1.01 feature ? fully compatible to standard mcs-51 microcontroller ? wide operating frequency up to 40mhz (for more detail, see ?HMS99C51S/52s/5 4s/56s/58s selection guide? on page 1) ? x2 speed improvement capability ( x2 mode : 6 clocks/machine cycle ) 20mhz @5v (equivalent to 40mhz @5v) ? isp(in-system programming) using standard v cc power supply ? boot rom contains low level flash programming routines and a default serial loader ? 4k/8k/16k/24k/32k bytes flash user program memory - byte write and block(2k, 8k bytes) erase ? 2k bytes flash boot loader ? 1 byte hardware security byte (hsb) ? 256 bytes ram ? 64k bytes external program memory space ? 64k bytes external data memory space ? four 8-bit ports ? three 16-bit timers / counters (timer2 with up/down counter feature) ?uart ? one clock output port ? programmable ale pin enable / disable (low emi ) ? six interrupt sources, two priority levels ? power saving idle and power down mode ? p-dip-40, p-lcc-44, p-mqfp-44 package ? temperature ranges : -40 c ~ 85 c description the flash memory increases eprom a nd rom functionality with in-circu it electrical erasure and program- ming. it contains 4k, 8k, 16k, 24k or 32k bytes of program memory. this memory is both parallel and serial in-system programmable(isp). the isp allows devices to alter their own program memory in the actual end product under software control through uart ports. a de fault serial loader(bootload er) program supports isp of the flash memory. the programming does not require external 12v programming voltage. the necessary high programming voltage is generated on-chip using the standard v cc pins of the microcontroller.
HMS99C51S/52s/54s/56s/58s sep. 2004 ver 1.01 3 block diagram ram 256 8 port 0 port 1 port 3 port 2 8-bit uart flash rom 4k/8k/16k/24k/ cpu t 0 t 1 i/o i/o i/o i/o t 2 boot 2k 8 hsb 1 x 8 rom 32k x 8
HMS99C51S/52s/54s/56s/58s 4 sep. 2004 ver 1.01 pin configuration 44-plcc pin configuration (top view) p0.4 / ad4 p0.5 / ad5 p0.6 / ad6 p0.7 / ad7 ea / v pp n.c.* ale / prog psen p2.7 / a15 p2.6 / a14 p2.5 / a13 p1.5 p1.6 p1.7 reset rxd / p3.0 n.c.* txd / p3.1 int0 / p3.2 int1 / p3.3 t0 / p3.4 t1 / p3.5 wr / p3.6 rd / p3.7 xtal2 xtal1 v ss n.c.* p2.0 / a8 p2.1 / a9 p2.2 / a10 p2.3 / a11 p2.4 / a12 p1.4 p1.3 p1.2 p1.1 / t2ex p1.0 / t2 n.c.* v cc p0.0 / ad0 p0.1 / ad1 p0.2 / ad2 p0.3 / ad3 6 5 4 3 2 1 44 43 42 41 40 18 19 20 21 22 23 24 25 26 27 28 39 38 37 36 35 34 33 32 31 30 29 7 8 9 10 11 12 13 14 15 16 17 index corner n.c.: no connection
HMS99C51S/52s/54s/56s/58s sep. 2004 ver 1.01 5 40-pdip pin configuration (top view) p0.4 / ad4 p0.5 / ad5 p0.6 / ad6 p0.7 / ad7 ea / v pp ale / prog psen p2.7 / a15 p2.6 / a14 p2.5 / a13 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 40 p2.4 / a12 p2.3 / a11 p2.2 / a10 p2.1 / a9 p2.0 / a8 p0.0 / ad0 p0.1 / ad1 p0.2 / ad2 p0.3 / ad3 v cc t2ex / p1.1 p1.2 p1.3 p1.4 t2 / p1.0 p1.5 p1.6 p1.7 reset rxd / p3.0 txd / p3.1 int0 / p3.2 int1 / p3.3 t0 / p3.4 t1 / p3.5 wr / p3.6 rd / p3.7 xtal2 xtal1 v ss 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1
HMS99C51S/52s/54s/56s/58s 6 sep. 2004 ver 1.01 44-mqfp pin configuration (top view) p0.4 / ad4 p0.5 / ad5 p0.6 / ad6 p0.7 / ad7 ea / v pp n.c.* ale / prog psen p2.7 / a15 p2.6 / a14 p2.5 / a13 p1.5 p1.6 p1.7 reset rxd / p3.0 n.c.* txd / p3.1 int0 / p3.2 int1 / p3.3 t0 / p3.4 t1 / p3.5 wr / p3.6 rd / p3.7 xtal2 xtal1 v ss n.c.* p2.0 / a8 p2.1 / a9 p2.2 / a10 p2.3 / a11 p2.4 / a12 p1.4 p1.3 p1.2 p1.1 / t2ex p1.0 / t2 n.c.* v cc p0.0 / ad0 p0.1 / ad1 p0.2 / ad2 p0.3 / ad3 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 n.c.: no connection
HMS99C51S/52s/54s/56s/58s sep. 2004 ver 1.01 7 logic symbol xtal1 xtal2 reset port 0 8-bit digital i/o port 1 8-bit digital i/o port 2 8-bit digital i/o port 3 8-bit digital i/o ea /v pp ale/prog psen v cc v ss
HMS99C51S/52s/54s/56s/58s 8 sep. 2004 ver 1.01 pin definitions and functions symbol pin number input/ output function plcc- 44 pdip- 40 mqfp- 44 p1.0-p1.7 2-9 2 3 1-8 1 2 40-44, 1-3 40 41 i/o port1 port 1 is an 8-bit bidirectional i/o port with internal pull-ups. port 1 pins that have 1s written to them are pulled high by the internal pull-up resistors and can be used as inputs. as inputs, port 1 pins that are externally pulled low will source current because of the pulls-ups (i il , in the dc characteristics). port1 also serves alternate functions of timer 2 as follows. p1.0 / t2, clock out : timer/counter 2 external count input, clock out p1.1 / t2ex :timer/counter 2 trigger input port1 receives the low-order address bytes during flash programming and verifying. p3.0-p3.7 11, 13-19 10-17 5, 7-13 i/o port 3 port 3 is an 8-bit bidirectional i/o port with internal pull-ups. port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors and can be used as inputs. as inputs, port 3 pins that are externally pulled low will source current because of the pulls-ups (i il , in the dc characteristics). port 3 also serves the special features of the 80c51 family, as listed below. 11 13 14 15 16 17 18 19 10 11 12 13 14 15 16 17 5 7 8 9 10 11 12 13 p3.0 / rxd p3.1 / txd p3.2 /int0 p3.3 / int1 p3.4 /t0 p3.5 /t1 p3.6 / wr p3.7 /rd receiver data input (asynchronous) or data input/output(synchronous) of serial interface 0 transmitter data output (asynchronous) or clock output (synchronous) of the serial interface 0 interrupt 0 input/timer 0 gate control interrupt 1 input/timer 1 gate control counter 0 input counter 1 input the write control signal latches the data byte from port 0 into the external data memory the read control signal enables the external data memory to port 0 xtal2 20 18 14 o xtal2 output of the invertin g oscillator amplifier.
HMS99C51S/52s/54s/56s/58s sep. 2004 ver 1.01 9 xtal1 21 19 15 i xtal1 input to the inverting oscillator amplifier and input to the internal clock generator circuits. to drive the device from an external clock source, xtal1 should be driven, while xtal2 is left unconnected. there are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is divided down by a divide-by-two flip-flop. minimum and maximum high and low times as well as rise and fall times specified in the ac characteristics must be observed. p2.0-p2.7 24-31 21-28 18-25 i/o port 2 port 2 is an 8-bit bidirectional i/o port with internal pull-ups. port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors and can be used as inputs. as inputs, port 2 pins that are externally pulled low will source current because of the pulls-ups (i il , in the dc characteristics). port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (movx @dptr). in this application it uses strong internal pull-ups when outputting 1s. during accesses to external data memory that use 8-bit addresses (movx @ri), port 2 emits the contents of the p2 special function register. some port 2 pins receive the high-order address bits during flash program, verify, and erase operations. psen 32 29 26 o the program store enable the read strobe to external program memory when the device is executing code from the external program memory. psen is activated twice each machine cycle, except that two psen activations are skipped during each access to external data memory. psen is not activated during fetches from internal program memory. reset 10 9 4 i reset a high level on this pin for two machine cycles while the oscillator is running re sets the device. the port pins will be driven to their reset condition when a minimum v ih voltage is applied w hether the oscillator is running or not. an internal diffused resistor to v ss permits power-on reset using only an external capacitor to v cc . symbol pin number input/ output function plcc- 44 pdip- 40 mqfp- 44
HMS99C51S/52s/54s/56s/58s 10 sep. 2004 ver 1.01 ale / prog 33 30 27 o the address latch enable / program pulse output pulse for latching the low byte of the address during an access to extern al memory. in normal operation, ale is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. note that one ale pulse is skipped during each access to external data memory. this pin is also the program pulse input (prog ) during eprom programming. if desired, ale operation can be disabled by setting bit 0 of sfr location 8e h . with this bit set, the pin is weakly pulled high. the ale disable feature will be terminated by reset. setting the ale-disable bit has no affect if the mi crocontroller is in external execution mode. ea / v pp 35 31 29 i external access enable / program supply voltage ea must be externally held low to enable the device to fetch code from external program memory locations 0000 h to ffff h . if ea is held high, the device executes from internal program memory unless the program counter contains an address greater than its internal memory size. this pin also receives the 12.75v programming supply voltage (v pp ) during eprom programming. note; however, that if any of the lock bits are programmed, ea will be internally latched on reset. p0.0-p0.7 36-43 32-39 30-37 i/o port 0 port 0 is an 8-bit open-drain bidirectional i/o port. port 0 pins that have 1s wr itten to them float and can be used as high-impedance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. in this application it uses strong internal pull-ups when emitting 1s. port 0 also receives and outputs the code bytes during program and verification respectively in the gms99x5x. external pull-up resistors are required during program verification. v ss 22 20 16 - circuit ground potential v cc 44 40 38 - supply terminal for all operating modes n.c. 1,12 23,34 -6,17 28,39 - no connection symbol pin number input/ output function plcc- 44 pdip- 40 mqfp- 44
HMS99C51S/52s/54s/56s/58s sep. 2004 ver 1.01 11 functional description the HMS99C51S/52s/54s/56s/58s are fully compatible to the standard 8051 microcontroller family. it is compatible with the general 8051 family, while ma intaining all architectural an d operational characteristics of the general 8051 family. figure 1 shows a block diagram of the HMS99C51S/52s/54s/56s/58s. figure 1. block diagram of the HMS99C51S/52s/54s/56s/58s flash 4k/8k/16k/ ram 256 osc & timing cpu timer 0 timer 1 timer 2 interrupt unit serial channel port 0 port 1 port 2 port 3 port 0 8-bit digit. i/o port 1 8-bit digit. i/o port 2 8-bit digit. i/o port 3 8-bit digit. i/o xtal1 xtal2 reset ea /v pp ale/prog psen boot 2k hsb 1 flash 24k/32k
HMS99C51S/52s/54s/56s/58s 12 sep. 2004 ver 1.01 cpu the HMS99C51S/52s/54s/56s/58s are efficient both as a controller and as an arithmetic processor. it has ex- tensive facilities for binary and bcd ar ithmetic and excels in its bit-handlin g capabilities. efficient use of pro- gram memory results from an instruction set consis ting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. with a 12 mhz crystal, 58% of the instructions are executed in 1.0 s (40mhz: 300ns). special function register psw reset value of psw is 00 h . bit function cy carry flag ac auxiliary carry flag (for bcd operations) f0 general purpose flag rs1 0 0 1 1 rs0 0 1 0 1 register bank select control bits bank 0 selected, data address 00 h - 07 h bank 1 selected, data address 08 h - 0f h bank 2 selected, data address 10 h - 17 h bank 3 selected, data address 18 h - 1f h ov overflow flag f1 general purpose flag p parity flag set/cleared by ha rdware each instruction cycle to indicate an odd/even number of "one" bits in the accumulator, i.e. even parity. cy ac f0 rs1 rs0 ov f1 p 76543210 lsb msb bit no. addr. d0 h psw
HMS99C51S/52s/54s/56s/58s sep. 2004 ver 1.01 13 special function registers all registers, except the progr am counter and the four general purpose register banks, reside in the special func- tion register area. the 28 special function registers (sfr) include pointers and registers that provide an interface between the cpu and the other on-chip peripherals. there are also 128 dir ectly addressable bits within the sfr area. all sfrs are listed in table 1, table 2, and table 3. in table 1 they are organized in numeric order of their addresses. in table 2 they are organized in groups which refer to the functional blocks of the HMS99C51S/52s/54s /56s/58s. table 3 illustrates the contents of the sfrs address register contents after reset address register contents after reset 80 h 81 h 82 h 83 h 84 h 85 h 86 h 87 h p0 1) sp dpl dph reserved reserved reserved pcon ff h 07 h 00 h 00 h xx h 2) xx h 2) xx h 2) 0xxx0000 b 2) 88 h 89 h 8a h 8b h 8c h 8d h 8e h 8f h tcon 1) tmod tl0 tl1 th0 th1 auxr0 ckcon 00 h 00 h 00 h 00 h 00 h 00 h xx h 2) xxxxxxx0 b 2) 90 h 91 h 92 h 93 h 94 h 95 h 96 h 97 h p1 1) reserved reserved reserved reserved reserved reserved reserved ff h 00 h xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) 98 h 99 h 9a h 9b h 9c h 9d h 9e h 9f h scon 1) sbuf reserved reserved reserved reserved reserved reserved 00 h xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) a0 h a1 h a2 h a3 h a4 h a5 h a6 h a7 h p2 1) reserved reserved reserved reserved reserved reserved reserved ff h xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) a8 h a9 h aa h ab h ac h ad h ae h af h ie 1) reserved reserved reserved reserved reserved reserved reserved 0x000000 b 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) b0 h b1 h b2 h b3 h b4 h b5 h b6 h b7 h p3 1) reserved reserved reserved reserved reserved reserved reserved ff h xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) b8 h b9 h ba h bb h bc h bd h be h bf h ip 1) reserved reserved reserved reserved reserved reserved reserved xx000000 b 2) xx h 2) xx h 2) xx h 2) xx h 2) xx 2) xx h 2) xx h 2) table 1. special function registers in numeric order of their addresses (cont?d)
HMS99C51S/52s/54s/56s/58s 14 sep. 2004 ver 1.01 c0 h c1 h c2 h c3 h c4 h c5 h c6 h c7 h reserved reserved reserved reserved reserved reserved reserved reserved xx h xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) c8 h c9 h ca h cb h cc h cd h ce h cf h t2con 1) t2mod rc2l 1) rc2h 1) tl2 1) th2 1) reserved reserved 00 h xxxxxx00 b 2) 00 h 00 h 00 h 00 h xx h 2) xx h 2) d0 h d1 h d2 h d3 h d4 h d5 h d6 h d7 h psw 1) fcon 3) reserved reserved reserved reserved reserved reserved ff h xxxx0000 b 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) d8 h d9 h da h db h dc h dd h de h df h reserved reserved reserved reserved reserved reserved reserved reserved xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) e0 h e1 h e2 h e3 h e4 h e5 h e6 h e7 h acc 1) reserved reserved reserved reserved reserved reserved reserved 00 h xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) e8 h e9 h ea h eb h ec h ed h ee h ef h reserved reserved reserved reserved reserved reserved reserved reserved xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) f0 h f1 h f2 h f3 h f4 h f5 h f6 h f7 h b 1) reserved reserved reserved reserved reserved reserved reserved 00 h xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) f8 h f9 h fa h fb h fc h fd h fe h ff h reserved reserved reserved reserved reserved reserved reserved reserved xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) 1) bit-addressable special function register. 2) x means that the value is indeterminate and the location is reserved. 3) fcon access is reserved for the isp software. address register contents after reset address register contents after reset table 1. special function registers in numeric order of their addresses (cont?d)
HMS99C51S/52s/54s/56s/58s sep. 2004 ver 1.01 15 block symbol name address contents after reset cpu acc b dph dpl psw sp accumulator b-register data pointer, high byte data pointer, low byte program status word register stack pointer e0 h 1) f0 h 1) 83 h 82 h d0 h 1) 81 h 1) bit-addressable special function register 00 h 00 h 00 h 00 h 00 h 07 h interrupt system ie ip interrupt enable register interrupt priority register a8 h 1) b8 h 1) 0x000000 b 2) xx000000 b 2) 2) x means that the value is indeterminate and the location is reserved ports p0 p1 p2 p3 port 0 port 1 port 2 port 3 80 h 1) 90 h 1) a0 h 1) b0 h 1) ff h ff h ff h ff h serial channels pcon 3) sbuf scon 3) this special function register is listed repeatedly since some bit of it also belong to other functional blocks power control register serial channel buffer reg. serial channel 0 control reg. 87 h 99 h 98 h 1) 0xxx0000 b 2) xx h 2) 00 h timer 0/ timer 1 tcon th0 th1 tl0 tl1 tmod timer 0/1 control register timer 0, high byte timer 1, high byte timer 0, low byte timer 1, low byte timer mode register 88 h 1) 8c h 8d h 8a h 8b h 89 h 00 h 00 h 00 h 00 h 00 h 00 h timer 2 t2con t2mod rc2h rc2l th2 tl2 auxr0 timer 2 control register timer 2 mode register timer 2 reload capture reg., high byte timer 2 reload capture reg., low byte timer 2, high byte timer 2, low byte aux. register 0 c8 h 1) c9 h cb h ca h cd h cc h 8e h 00 h 00 h 00 h 00 h 00 h 00 h xxxxxxx0 b 2) power saving modes pcon 3) power control register 87 h 0xxx0000 b 2) flash fcon 4) 4) this special function register is reserved for the isp software. flash control register d1 h xxxx0000 b 2) table 2. special function registers - functional blocks
HMS99C51S/52s/54s/56s/58s 16 sep. 2004 ver 1.01 address register bit 76543210 80 h p0 81 h sp 82 h dpl 83 h dph 87 h pcon smod - - - gf1 gf0 pde idle 88 h tcon tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 89 h tmod gate c/t m1 mt gate c/t m1 m0 8a h tl0 8b h tl1 8c h th0 8d h th1 8e h auxr0 - ------a0 8f h ckcon - ------x2 90 h p1 98 h scon sm0 sm1 sm2 ren tb8 rb8 ti ri 99 h sbuf a0 h p2 a8 h ie ea - et2 es et1 ex1 et0 ex0 b0 h p3 b8 h ip - - pt2 ps pt1 px1 pt0 px0 table 3. contents of sfrs, sfrs in numeric order sfr bit and byte addressable sfr not bit addressable - : this bit loca tion is reserved
HMS99C51S/52s/54s/56s/58s sep. 2004 ver 1.01 17 address register bit 76543210 c8 h t2con tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/rl2 c9 h t2mod ------ t2oe ? dcen ca h rc2l cb h rc2h cc h tl2 cd h th2 d0 h psw cy ac f0 rs1 rs0 ov f1 p d1 h fcon frsel2 frsel1 frsel0 erasesel enboot introm_en pgmsel1 pgmsel0 e0 h acc f0 h b table 3. contents of sfrs, sfrs in numeric order (cont?d) a0 8e h 0 : enable ale signal (generated ale signal) c9 h 1 : disable ale signal (not generated ale signal) t2oe 0 : disable timer2 output 1 : enable timer2 output t2oe : timer2 output enable bit a0 : ale signal disable bit x2 8f h 0 : select 12 clock periods per machine cycle 1 : select 6 clock periods per machine cycle x2 : cpu & peripheral clock select bit
HMS99C51S/52s/54s/56s/58s 18 sep. 2004 ver 1.01 sfr bit and byte addressable sfr not bit addressable - : this bit location is reserved
HMS99C51S/52s/54s/56s/58s sep. 2004 ver 1.01 19 x2 mode the HMS99C51S/52s/54s/56s/58s core needs only 6 clock periods per machine cycle in x2 mode. this fea- ture called ?x2? provides the following advantages: ? divide frequency crystals by 2 (cheaper crystals) while keeping same cpu power. ? save power consumption while keeping sa me cpu power (oscilla tor power saving). ? save power consumption by dividi ng dynamically operating frequency by 2 in operating and idle modes. ? increase cpu power by 2 while keeping same crystal frequency. in order to keep the original c51 co mpatibility, a divider by 2 is insert ed between the xtal 1 signal and the main clock input of the core (phase generato r). this divider may be disabled by software. x2 mode description the clock for the whole circuit and peripheral is first divided by two before being used by the cpu core and peripherals. this allows any cyclic ratio to be accepted on xtal1 input. in x2 mode, as this divider is bypassed, the signals on xtal1 must have a cy clic ratio between 40 to 60%. figure 2. shows the clock generation block diagram. x2 bit is validated on xtal1 2 rising edge to avoid glitches when switching from x2 to std mode. figure 3. shows the mode switching waveforms: figure 2. clock generation diagram the x2 bit in the ckcon register allows to switch from 12 clock cycles per instruction to 6 clock cycles and vice versa. at reset, the standard speed is activated (std mode). setting this bit activates the x2 feature(x2 mode). caution in order to prevent any incorrect oper ation while operating in x2 mode, user must be aware that all peripherals using clock frequency as time reference (uart, timers) wi ll have their time reference divided by two. for ex- ample a free running timer generating an interrupt every 30 ms will then generate an interrupt every 15 ms. uart with 2400 baud rate will have 4800 baud rate. f osc 2 x2 state machine: 6 clock cycles ckcon register 1 0 cpu control xtal1
HMS99C51S/52s/54s/56s/58s 20 sep. 2004 ver 1.01 figure 3. mode switching waveforms . xtal1 cpu clock xtal1:2 x2 mode x2 bit std mode std mode
HMS99C51S/52s/54s/56s/58s sep. 2004 ver 1.01 21 timer / counter 0 and 1 timer/counter 0 and 1 can be used in four operating modes as listed in table 4: in the ?timer? function (c/t = ?0?) the register is incremented every machine cycle. therefore the count rate is f osc /12. in the ?counter? function the register is incremented in response to a 1-to-0 transition at its corresponding ex- ternal input pin (p3.4/t0, p3.5/t1). since it takes two machine cycles to detect a falling edge the max. count rate is f osc /24. external inputs int0 and int1 (p3.2, p3.3) can be programmed to function as a gate to facilitate pulse width measurements. figure 4 illustrates the input clock logic. figure 4. timer/counter 0 and 1 input clock logic mode description tmod input clock gate c/t m1 m0 internal external (max.) 0 8-bit timer/co unter with a divide-by-32 prescaler xx0 0f osc (12 32) f osc (24 32) 1 16-bit timer/counter x x 0 1 f osc 12 f osc 24 2 8-bit timer/ counter with 8-bit auto-reload xx1 0 f osc 12 f osc 24 3 timer/counter 0 used as one 8-bit timer/counter and one 8-bit timer timer 1 stops xx1 1 f osc 12 f osc 24 table 4. timer/counter 0 and 1 operating modes f osc 12 tmod f osc 12 p3.4/t0 p3.5/t1 max. f osc /24 c/t =1 1 tcon tr0 / 1 tmod gate & p3.2 / int0 p3.3 / int1 timer 0/1 input clock 0 1
HMS99C51S/52s/54s/56s/58s 22 sep. 2004 ver 1.01 timer 2 timer 2 is a 16-bit timer/counter with an up/down count feat ure. it can operate either as timer or as an event counter which is selected by bit c/t2 (t2con.1). it has three operating modes as shown in table 5. note: = falling edge mode t2con t2m od t2c on p1. 1/ t2 ex remarks input clock rclk or tclk cp/ rl2 tr2 dce n exe n2 internal external (p1.0/t2) 16-bit auto- reload 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 1 x x x 0 1 reload upon over- flow reload trigger (falling edge) down counting up counting f osc 12 max. f osc 24 16-bit capture 0 0 1 1 1 1 x x 0 1 x 16 bit timer/ counter (only up- counting) capture th2,tl2 rc2h,rc2l f osc 12 max. f osc 24 baud rate generator 1 1 x x 1 1 x x 0 1 x no overflow interrupt request (tf2) extra external interrupt (?timer 2?) f osc 12 max. f osc 24 off x x 0 x x x timer 2 stops - - table 5. timer/counter 2 operating modes
HMS99C51S/52s/54s/56s/58s sep. 2004 ver 1.01 23 serial interface (uart) the serial port is full duplex and can operate in four modes (one synchronous mode, three asynchronous modes) as illustrated in table 6. the possible baud rates can be calculated using the formulas given in table 7. mode scon baudrate description sm0 sm1 000 serial data enters and exits through rxd. txd outputs the shift cloc k. 8-bit are transmit- ted/received (lsb first) 1 0 1 timer 1/2 overflow rate 8-bit uart 10 bits are transmitted (through txd) or received (rxd) 210 or 9-bit uart 11 bits are transmitted (txd) or received (rxd) 3 1 1 timer 1/2 overflow rate 9-bit uart like mode 2 except the variable baud rate table 6. uart operating modes baud rate derived from interface mode baudrate oscillator 0 2 timer 1 (16-bit timer) (8-bit timer with 8-bit auto reload) 1,3 1,3 timer 2 1,3 table 7. formulas for calculating baud rates f osc 12 ------------ f osc 32 ------------ f osc 64 ------------ f osc 12 ------------ 2 smod 64 ------------------ f osc 2 smod 32 ------------------ timer 1 overflow () 2 smod 32 ------------------ f osc 12 256 th1 () ? [] -------------------------------------------------- f osc 32 65536 rc2h rc2l , () ? [] --------------------------------------------------------------------------------- -
HMS99C51S/52s/54s/56s/58s 24 sep. 2004 ver 1.01 interrupt system the HMS99C51S/52s/54s/56s/58s provide 6 (above 8k bytes rom version) interrupt sources with two pri- ority levels. figure 5 gives a general overview of the in terrupt sources and illustrates the request and control flags. figure 5. interrupt request sources pt0 ip.1 pt1 ip.3 pt2 ip.5 ps ip.4 px0 ip.0 px1 ip.2 ea ie.7 et0 ie.1 et1 ie.3 et2 ie.5 es ie.4 ex0 ie.0 ex1 ie.2 tf0 tcon.5 tf1 tcon.7 1 tf2 t2con.7 exf2 t2con.6 1 ri scon.0 ti scon.1 ie0 tcon.1 ie1 tcon.3 it0 tcon.0 it1 tcon.2 p3.2/ int0 p3.3/ int1 exen2 t2con.3 p1.1/ t2ex timer 2 overflow timer 0 overflow timer 1 overflow : low level triggered : falling edge triggered low priority high priority uart
HMS99C51S/52s/54s/56s/58s sep. 2004 ver 1.01 25 a low-priority interrupt can itself be interrupted by a hi gh-priority interrupt, but not by another low priority in- terrupt. a high-priority interrupt cannot be interrupted by any other interrupt source. if two requests of different priority level are received si multaneously, the request of higher priority is serviced. if requests of the same priority are received simultan eously, an internal polling se quence determines which re- quest is serviced. thus within each pr iority level there is a second priority structure determin ed by the polling sequence as shown in table 9. source (request flags) vectors vector address reset ie0 tf0 ie1 tf1 ri + ti tf2 + exf2 reset external interrupt 0 timer 0 interrupt external interrupt 1 timer 1 interrupt serial port interrupt timer 2 interrupt 0000 h 0003 h 000b h 0013 h 001b h 0023 h 002b h table 8. interrupt sources and their corresponding interrupt vectors interrupt source priority external interrupt 0 timer 0 interrupt external interrupt 1 timer 1 interrupt serial channel timer 2 interrupt ie0 tf0 ie1 tf1 ri + ti tf2 + exf2 high low table 9. interrupt priority-within-level
HMS99C51S/52s/54s/56s/58s 26 sep. 2004 ver 1.01 power saving modes two power down modes are available, the idle mode and power down mode. the bits pde and idle of the register pcon select the power down mode or the idle mode, respectively. if the power down mode and the idle mode are set at the same time, the power down mode takes precedence. table 10 gives a general overview of the power saving modes. in the power down mode of operation, v cc can be reduced to minimize power consumption. it must be ensured, however, that v cc is not reduced before the power down mode is invoked, and that v cc is restored to its normal operating level, before the power down mode is terminated. the reset signal that terminates the power down mode also restarts the os cillator. the reset should no t be activated before v cc is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize (similar to power-on reset). mode entering instruction example leaving by remarks idle mode orl pcon, #01h - enabled interrupt - hardware reset cpu is gated off cpu status registers maintain their data. peripherals are active power-down mode orl pcon, #02h hardware reset oscillator is stopped, contents of on- chip ram and sfr?s are maintained (leaving power down mode means redefinition of sfr contents). table 10. power saving modes overview
HMS99C51S/52s/54s/56s/58s sep. 2004 ver 1.01 27 electrical characteristics absolute maximum ratings ambient temperature under bias (t a )...................................................................................... -40 to + 85 c storage temperature (t st )...................................................................................................... -65 to + 150 c voltage on v cc pins with respect to ground (v ss ) ................................................................. -0.5v to 6.5v voltage on any pin with respect to ground (v ss ) ..........................................................-0.5v to v cc + 0.5v input current on any pin during overload condition..... .......................................................-10ma to +10ma absolute sum of all input currents during overload co ndition...........................................................|100ma| power dissipation .............................................................................................................. ............ ..... 200mw note: stresses above those listed under ?absolute maximu m ratings? may cause permanent damage of the de- vice. this is a stress rating only and functional operat ion of the device at these or any other conditions above those indicated in the operational sect ions of this specification is not im plied. exposure to absolute maximum rat- ing conditions for longer periods may affect device reliability. during overload conditions (v in > v cc or v in < v ss ) the voltage on v cc pins with respect to ground (v ss ) must not exceed the values defined by the absolute maxi- mum ratings.
HMS99C51S/52s/54s/56s/58s 28 sep. 2004 ver 1.01 dc characteristics dc characteristics for HMS99C51S/52s/54s/56s/58s v cc = 5v + 10%, -15%, v ss =0v, t a = -40 c to 85 c parameter symbol limit values un it test conditions min. max. input low voltage (except ea , reset) v il -0.5 0.2v cc - 0.1 v v cc = 5.5v input low voltage (ea )v il1 -0.5 0.2v cc - 0.1 v v cc = 5.5v input low voltage (reset) v il2 -0.5 0.2v cc + 0.1 v v cc = 5.5v input high voltage (except xtal1, ea , reset) v ih 0.2v cc + 0.9 v cc + 0.5 v v cc = 4.5v input high voltage to xtal1 v ih1 0.7v cc v cc + 0.5 v v cc = 4.5v input high voltage to ea , reset v ih2 0.6v cc v cc + 0.5 v v cc = 4.5v output low voltage (ports 1, 2, 3) v ol -0.45vv cc = 5.5v, i ol = 1.6ma 1) output low voltage (port 0, ale, psen ) v ol1 -0.45vv cc = 5.5v, i ol = 3.2ma 1) output high voltage (ports 1, 2, 3) v oh 2.4 0.9v cc -v v cc = 4.5v, i oh = -80 a v cc = 4.5v, i oh = -10 a output high voltage (port 0 in external bus mode, ale, psen ) v oh1 2.4 0.9v cc -v v cc = 4.5v, i oh = -800 a 2) v cc = 4.5v, i oh = -80 a 2) logic 0 input current (ports 1, 2, 3) i il -10 -65 av in = 0.45v logical 1-to-0 transition cur- rent (ports 1, 2, 3) i tl -65 -650 av in = 2.0v input leakage current (port 0, ea ) i li - 1 a0.45 < v in < v cc pin capacitance c io - 10 pf f c = 1mhz t a = 25 c power supply current: active mode, 4mhz 3) idle mode, 4mhz 4) active mode, 24 mhz 4) idle mode, 24mhz 4) active mode, 40 mhz 4) idle mode, 40 mhz 4) power down mode 4) i cc i cc i cc i cc i cc i cc i pd - 8 4 25 10 30 15 50 ma ma ma ma ma ma ua v cc = 5v 4) v cc = 5v 5) v cc = 5v 4) v cc = 5v 5) v cc = 5v 4) v cc = 5v 5) v cc = 5v 6)
HMS99C51S/52s/54s/56s/58s sep. 2004 ver 1.01 29 1) capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the v ol of ale and port 3. the noise is due to external bus capacit ance discharging into the port 0 and port 2 pins when these pins make 1-to-0 tran- sitions during bus operation. in t he worst case(capacitive loading: > 50pf at 3.3v, > 100pf at 5v), the noise pulse on ale line may exceed 0.8v. in such cases it may be desirable to qual ify ale with a schmitt-trigger, or use an address latch with a schmitt-trigger strobe input. 2) capacitive loading on ports 0 and 2 may cause the v oh on ale and psen to momentarily fall below the 0.9v cc specifica- tion when the address lines are stabilizing. 3) i cc max. at other frequencies is given by: active mode: i cc = 1.27 f osc + 5.73 idle mode: i cc = 0.28 f osc + 1.45 (except otp devices) where f osc is the oscillator frequency in mhz. i cc values are given in ma and measured at v cc = 5v. 4) i cc (active mode) is measured with: xtal1 driven with t clch , t chcl = 5ns, v il = v ss + 0.5v, v ih = v cc - 0.5v; xtal2 = n.c.; ea = port0 = reset = v cc ; all other pins are disconnected. i cc would be slightly higher if a cr ystal oscillator is used (appr. 1ma). 5) i cc (idle mode) is measured with all output pi ns disconnected and with all peripherals disabled; xtal1 driven with t clch , t chcl = 5ns, v il = v ss + 0.5v, v ih = v cc - 0.5v; xtal2 = n.c.; reset = ea = v ss ; port0 = v cc ; all other pins are disconnected; 6) i pd (power down mode) is meas ured under following conditions: ea = port0 = v cc ; reset = v ss ; xtal2 = n.c.; xtal1 = v ss ; all other pins are disconnected.
HMS99C51S/52s/54s/56s/58s 30 sep. 2004 ver 1.01 ac characteristics explanation of the ac symbols each timing symbol has 5 characters. the first character is always a ?t? (stand for time). the other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. the following is a list of all the character s and what they stand for. ac characteristics for HMS99C51S/52s/54s/56s/58s (12mhz version) external program memory characteristics ? interfacing the HMS99C51S/52s/54s/56s/58s to devices with fl oat times up to 75 ns is permi ssible. this limited bus conten- tion will not cause any damage to port 0 drivers. v cc = 5v : v cc = 5v + 10%, ? 15%, v ss = 0v, t a = -40 c to 85 c (c l for port 0, ale and psen outputs = 100pf, c l for all other outputs = 80pf) variable clock : vcc = 5v : 1/t clcl = 3.5 mhz to 12 mhz parameter symbol 12 mhz oscillator variable oscillator 1/t clcl = 3.5 to 12mhz unit min. max. min. max. ale pulse width t lhll 127 - 2t clcl -40 - ns address setup to ale t avll 43 - t clcl -40 - ns address hold after ale t llax 30 - t clcl -53 - ns ale low to valid instruction in t lliv - 233 - 4t clcl -100 ns ale to psen t llpl 58 - t clcl -25 - ns psen pulse width t plph 215 - 3t clcl -35 - ns psen to valid instruction in t pliv - 150 - 3t clcl -100 ns input instruction hold after psen t pxix 0- 0 - ns input instruction float after psen t pxiz ? -63 -t clcl -20 ns address valid after psen t pxav ? 75 - t clcl -8 - ns address to valid instruction in t aviv - 302 - 5t clcl -115 ns address float to psen t azpl 0- 0 - ns a: address c: clock d: input data h: logic level high i: instruction (program memory contents) l: logic level low, or ale p: psen q: output data r: rd signal t: time v: valid w: wr signal x: no longer a valid logic level z: float for example, t avll = time from address valid to ale low t llpl = time from ale low to psen low
HMS99C51S/52s/54s/56s/58s sep. 2004 ver 1.01 31 ac characteristics for HMS99C51S/52s/54s/56s/58s (12mhz) external data memo ry characteristics advance information (12mhz) external clock drive parameter symbol 12 mhz oscillator variable oscillator 1/t clcl = 3.5 to 12mhz unit min. max. min. max. rd pulse width t rlrh 400 - 6t clcl -100 - ns wr pulse width t wlwh 400 - 6t clcl -100 - ns address hold after ale t llax2 53 - t clcl -30 - ns rd to valid data in t rldv - 252 - 5t clcl -165 ns data hold after rd t rhdx 0- 0 - ns data float after rd t rhdz -97 -2t clcl -70 ns ale to valid data in t lldv - 517 - 8t clcl -150 ns address to valid data in t avdv - 585 - 9t clcl -165 ns ale to wr or rd t llwl 200 300 3t clcl -50 3t clcl +50 ns address valid to wr or rd t avwl 203 - 4t clcl -130 - ns wr or rd high to ale high t whlh 43 123 t clcl -40 t clcl +40 ns data valid to wr transition t qvwx 33 - t clcl -50 - ns data setup before wr t qvwh 433 - 7t clcl -150 - ns data hold after wr t whqx 33 - t clcl -50 - ns address float after rd t rlaz -0 - 0 ns parameter symbol variable oscillator (freq. = 3.5 to 12mhz) unit min. max. oscillator period (v cc =5v) t clcl 83.3 285.7 ns high time t chcx 20 t clcl - t clcx ns low time t clcx 20 t clcl - t chcx ns rise time t clch -20ns fall time t chcl -20ns
HMS99C51S/52s/54s/56s/58s 32 sep. 2004 ver 1.01 ac characteristics for HMS99C51S/52s/54s/56s/58s (24mhz version) v cc = 5v + 10%, ? 15%, v ss = 0v, t a = -40 c to 85 c (c l for port 0. ale and psen outputs = 100pf; c l for all other outputs = 80pf) external program memory characteristics ? interfacing the HMS99C51S/52s/54s/56s/58s to devices with fl oat times up to 35 ns is permi ssible. this limited bus conten- tion will not cause any damage to port 0 drivers. parameter symbol 24 mhz oscillator variable oscillator 1/t clcl = 3.5 to 24mhz unit min. max. min. max. ale pulse width t lhll 43 - 2t clcl -40 - ns address setup to ale t avll 17 - t clcl -25 - ns address hold after ale t llax 17 - t clcl -25 - ns ale low to valid instruction in t lliv -80 -4t clcl -87 ns ale to psen t llpl 22 - t clcl -20 - ns psen pulse width t plph 95 - 3t clcl -30 - ns psen to valid instruction in t pliv -60 -3t clcl -65 ns input instruction hold after psen t pxix 0- 0 - ns input instruction float after psen t pxiz ? -32 -t clcl -10 ns address valid after psen t pxav ? 37 - t clcl -5 - ns address to valid instruction in t aviv - 148 - 5t clcl -60 ns address float to psen t azpl 0- 0 - ns
HMS99C51S/52s/54s/56s/58s sep. 2004 ver 1.01 33 ac characteristics for hms9 9c51s/52s/54s/56s/58s(24mhz) external data memo ry characteristics advance information (24mhz) external clock drive parameter symbol 24 mhz oscillator variable oscillator 1/t clcl = 3.5 to 24mhz unit min. max. min. max. rd pulse width t rlrh 180 - 6t clcl -70 - ns wr pulse width t wlwh 180 - 6t clcl -70 - ns address hold after ale t llax2 15 - t clcl -27 - ns rd to valid data in t rldv - 118 - 5t clcl -90 ns data hold after rd t rhdx 0- 0 - ns data float after rd t rhdz -63 -2t clcl -20 ns ale to valid data in t lldv - 200 - 8t clcl -133 ns address to valid data in t avdv - 220 - 9t clcl -155 ns ale to wr or rd t llwl 75 175 3t clcl -50 3t clcl +50 ns address valid to wr or rd t avwl 67 - 4t clcl -97 - ns wr or rd high to ale high t whlh 17 67 t clcl -25 t clcl +25 ns data valid to wr transition t qvwx 5-t clcl -37 - ns data setup before wr t qvwh 170 - 7t clcl -122 - ns data hold after wr t whqx 15 - t clcl -27 - ns address float after rd t rlaz -0 - 0 ns parameter symbol variable oscillator (freq. = 3.5 to 24mhz) unit min. max. oscillator period t clcl 41.7 285.7 ns high time t chcx 12 t clcl - t clcx ns low time t clcx 12 t clcl - t chcx ns rise time t clch -12ns fall time t chcl -12ns
HMS99C51S/52s/54s/56s/58s 34 sep. 2004 ver 1.01 ac characteristics for hms99c51 s/52s/54s/56s/58s(40mhz version) v cc = 5v + 10%, ? 15%, v ss = 0v, t a = -40 c to 85 c (c l for port 0, ale and psen outputs = 100pf, c l for all other outputs = 80pf) external program memory characteristics ? interfacing the HMS99C51S/52s/54s/56s/58s to devices with fl oat times up to 20 ns is permi ssible. this limited bus conten- tion will not cause any damage to port 0 drivers. parameter symbol 40 mhz oscillator variable oscillator 1/t clcl = 3.5 to 40mhz unit min. max. min. max. ale pulse width t lhll 40 - 2t clcl ? 20 - ns address setup to ale t avll 10 - t clcl ? 20 - ns address hold after ale t llax 10 - t clcl ?20 -ns ale low to valid instruction in t lliv -56 -4t clcl ? 65 ns ale to psen t llpl 15 - t clcl ? 15 - ns psen pulse width t plph 80 - 3t clcl ? 20 - ns psen to valid instruction in t pliv -35 -3t clcl ? 55 ns input instruction hold after psen t pxix 0- 0 - ns input instruction float after psen t pxiz ? -20 -t clcl ? 10 ns address valid after psen t pxav ? 25 - t clcl ? 5- ns address to valid instruction in t aviv -91 -5t clcl ? 60 ns address float to psen t azpl 0- 0 - ns
HMS99C51S/52s/54s/56s/58s sep. 2004 ver 1.01 35 ac characteristics for hms9 9c51s/52s/54s/56s/58s(40mhz) external data memo ry characteristics advance information (40mhz) external clock drive parameter symbol at 40 mhz clock variable clock 1/t clcl = 3.5 to 40mhz unit min. max. min. max. rd pulse width t rlrh 132 - 6t clcl -50 - ns wr pulse width t wlwh 132 - 6t clcl -50 - ns address hold after ale t llax2 10 - t clcl -20 - ns rd to valid data in t rldv -81 -5t clcl -70 ns data hold after rd t rhdx 0- 0 - ns data float after rd t rhdz -46 -2t clcl -15 ns ale to valid data in t lldv - 153 - 8t clcl -90 ns address to valid data in t avdv - 183 - 9t clcl -90 ns ale to wr or rd t llwl 71 111 3t clcl -20 3t clcl +20 ns address valid to wr or rd t avwl 66 - 4t clcl -55 - ns wr or rd high to ale high t whlh 10 40 t clcl -20 t clcl +20 ns data valid to wr transition t qvwx 5-t clcl -25 - ns data setup before wr t qvwh 142 - 7t clcl -70 - ns data hold after wr t whqx 10 - t clcl -20 - ns address float after rd t rlaz -0 - 0 ns parameter symbol variable oscillator (freq. = 3.5 to 40mhz) unit min. max. oscillator period t clcl 30.3 285.7 ns high time t chcx 11.5 t clcl - t clcx ns low time t clcx 11.5 t clcl - t chcx ns rise time t clch -5ns fall time t chcl -5ns
HMS99C51S/52s/54s/56s/58s 36 sep. 2004 ver 1.01 figure 6. external program memory read cycle t lhll t pxav t pxiz t pxix t llax t lliv t pliv t plph t azpl t llpl t avll a0-a7 instr. in a0-a7 a8-a15 a8-a15 t aviv ale psen port 0 port 2
HMS99C51S/52s/54s/56s/58s sep. 2004 ver 1.01 37 figure 7. external data memory read cycle figure 8. external data memory write cycle t lhll p2.0-p2.7 or a8-a15 from dph a8-a15 from pch ale psen port 0 port 2 rd t llwl data in a0-a7 from pcl instr. in a0-a7 from t llax2 t avwl t avll t avdv t rlaz t lldv t rlrh t rldv t rhdx t rhdz t whlh ri or dpl t lhll p2.0-p2.7 or a8-a15 from dph a8-a15 from pch ale psen port 0 port 2 wr t llwl data out a0-a7 from pcl instr. in a0-a7 from t llax2 t avwl t avll t wlwh t whqx t whlh ri or dpl t qvwx t qvwh
HMS99C51S/52s/54s/56s/58s 38 sep. 2004 ver 1.01 figure 9. ac testing: input, output waveforms figure 10. float waveforms figure 11. external clock cycle ac inputs during testing are driven at v cc ? 0.5v for a logic ?1? and 0.45v for a logic ?0?. 0.2v cc + 0.9 0.2v cc ? 0.1 test points v cc ? 0.5v 0.45v timing measurements are made a v ihmin for a logic ?1? and v ilmax for a logic ?0?. v load + 0.1 v load ? 0.1 timing reference points 0.2v cc ? 0.1 v oh ? 0.1 v ol + 0.1 v load for timing purposes a port pin is no longer floating when a 100mv change from load voltage i ol / i oh 20ma. occurs and begins to float when a 100mv change from the loaded v oh / v ol level occurs. t chcl t clch t chcx t clcl t clcx 0.2 v cc ? 0.1 0.7 v cc v cc ? 0.5v 0.45v
HMS99C51S/52s/54s/56s/58s sep. 2004 ver 1.01 39 oscillator circuit figure 12. recommended oscillator circuits oscillation circuit is designed to be us ed either with a ceramic resonator or crystal oscillator. since each crystal and ceramic resonator have their own characteristics, the user should cons ult the crystal ma nufacturer for ap- propriate values of external components. xtal2 p-lcc-44/pin 20 p-dip-40/pin 18 m-qfp-44/pin 14 xtal1 p-lcc-44/pin 21 p-dip-40/pin 19 m-qfp-44/pin 15 crystal oscillator mode driving from external source xtal2 p-lcc-44/pin 20 p-dip-40/pin 18 m-qfp-44/pin 14 xtal1 p-lcc-44/pin 21 p-dip-40/pin 19 m-qfp-44/pin 15 external oscillator signal n.c. c2 c1 c1, c2 = 30pf 10pf for crystals for ceramic resonators, contact resonator manufacturer.
HMS99C51S/52s/54s/56s/58s 40 sep. 2004 ver 1.01 plastic package p-lcc-44 (plastic leaded chip-carrier) 0.180 0.165 unit: inch 44plcc 0.012 0.0075 0.120 0.090 0.032 0.026 0.630 0.590 min. 0.020 0.656 0.650 0.695 0.685 0.656 0.650 0.695 0.685 0.050 bsc 0.021 0.013
HMS99C51S/52s/54s/56s/58s sep. 2004 ver 1.01 41 plastic package p-dip-40 (plastic dual in-line package) unit: inch 2.075 2.045 0.200 max. 0.022 0.015 0.065 0.045 0.100 bsc 0.550 0.530 0.600 bsc 0-15 0 . 0 1 2 0 . 0 0 8 40dip 0.140 0.120 min. 0.015
HMS99C51S/52s/54s/56s/58s 42 sep. 2004 ver 1.01 plastic package p-mpqf-44 (plastic metric quad flat package) 2.35 max. see detail "a" 1.03 0.73 0-7 0.25 0.10 1.60 ref detail "a" unit: mm 0.45 0.30 0.80 bsc 2.10 1.95 44mqfp 0 . 1 3 0 . 2 3 10.10 9.90 13.45 12.95 10.10 9.90 13.45 12.95
HMS99C51S/52s/54s/56s/58s sep. 2004 ver 1.01 43 flash memory overview the flash memory increases eprom a nd rom functionality with in-circu it electrical erasure and program- ming. it contains 4k, 8k, 16k, 24k or 32k bytes of program memory. this memory is both parallel and serial in-system programmable (isp). isp allows devices to alter their own program memory in the actual end product under software control. a default serial loader (bootl oader) program allows isp of the flash. the programming does not require 12v external programming voltage. the necessary high programming voltage is generated on- chip using the standard v cc pins of the microcontroller. features ? flash memory internal program memory. ? default loader in boot rom allows programming vi a the serial port without the need of a user pro- vided loader. ? up to 64k byte external program memory if the internal program memory is disabled (ea = 0). ? programming and erase voltage with standard 5v v cc supply. ? read/programming/erase: - programming time per byte : 20us (tbd) - block erase/total erase time : 200ms (tbd) - typical programming time (32k bytes) is 10s at isp mode (tbd) ? parallel programming with at mel/philips chip compatible har dware interface to programmer ? programmable security fo r the code in the flash ? endurance : 10,000 cycles (tbd) ? data retention : 10 years (tbd) flash programming and erasure there are three methods of pr ogramming the flash memory: ? first, the on-chip isp bootloade r may be invoked which will use low level routines to progr am. the interface used for serial downloadi ng of flash memory is the uart. ? second, the flash may be progra mmed or erased in the end-user application by calling low level routines through a common entry point in the boot rom. ? third, the flash may be programmed using the parallel method by using conventional eprom programmer. the commercially available programme rs need to have support for the HMS99C51S/ 52s/54s/56s/58s. the bootloader rout ines are located in the boot rom.
HMS99C51S/52s/54s/56s/58s 44 sep. 2004 ver 1.01 flash memory architecture HMS99C51S/52s/54s/56s/58s feature two on-chip flash memories: ? flash memory fm0: 4k/8k/16k/24k/32k bytes user program memory ? flash memory fm1: 2k bytes for bootloader. the fm0 and fm1 can be programmed by both para llel programming and serial in-system program- ming. the isp mode is detailed in th e "in-system programming" section. fm0 memory architecture ? 4k/8k/16k/24k/32k bytes user program memory ? hardware security bits (hsb) user space this space is composed of a 4k/8 k/16k/24k/32k bytes flash memory. HMS99C51S/52s has only sectors of 2k byte unit block, and hms99c54s/56s/58s has 4 sectors of 2k byte unit block and other sectors of 8k byte unit block. it contains the user?s application code. hardware security byte the hardware security byte space is a part of hsb and has a size of 1 byte. reserved 4k/8k/16k/24k/32k bytes user application (fm0) isp + flash management fm1(2k bytes): boot loader f800 h ffff h 7fff h 0000 h hsb (1byte) 807f h
HMS99C51S/52s/54s/56s/58s sep. 2004 ver 1.01 45 cross flash memory access description the fm0 and fm1 memory can be programmed by parallel programming. the fm0 memory can be programmed from fm1. but, programming fm1 from fm0 or from external memory is impossible. fm1 memory can be programmed only by parallel programming. overview of fm0 operations the cpu interfaces to the flash memory through the fcon register of sfr fcon register is used to: ? select register for operation of flash access (frsel[2:0]) ? erase mode select (erasesel) ? enable boot flash (enboot) ? 64k bytes internal rom access (introm_en) ? program mode select (pgmsel) mapping of the memory space by default, the user space is accessed by movc instruction for read only. the other memory spaces (user, boot, hsb) are made accessible in the code se gment by programming bits introm_en, enboot in fcon register in advance. a movc instruction is then used for reading these spaces in accordance with address of table 12. action fm0 (user flash) fm1 (boot flash) fm0 read ok - write/erase - - fm1 read ok ok write/erase ok - table 11. cross flash memory access region addr. 15 addr. 14~11 addr. 10~7 addr. 6~0 hsb(1 bytes) 1 0000 0111 1111 boot(2k bytes) 1111 variable variable user(32k bytes) 0 variable variable variable table 12. fm0 blocks select bits code executing from
HMS99C51S/52s/54s/56s/58s 46 sep. 2004 ver 1.01 flash registers and memory map the HMS99C51S/52s/54s/56s/58s flash memory uses several registers for its management: ? hardware registers can only be accessed through the parallel programming modes which are han- dled by the parallel programmer. hardware register the only hardware register of the HMS99C51S/52s/ 54s/56s/58s is called hardware security byte(hsb). 1 : unprogrammed 0 : programmed note: hsb can be read but can not be programmed in isp mode and only programmable by specific tools. - - - bljb_en bljb lb2 lb1 lb0 table 13. hardware security byte(hsb) bit no bit mnemonic description 7~5 - reserved 4 bljn_en enable bljb bit 1 : bljb is enabled for isp mode 0 : bljb is disabled. (after finishing of download, must be programmed.) 3 bljb boot loader jump bit 1 : start the user?s application on next reset at address 0000 h 0 : start the boot loader at address f800 h (default). 2~0 lb2~0 user memory lock bits see table 14
HMS99C51S/52s/54s/56s/58s sep. 2004 ver 1.01 47 flash memory lock bits the three lock bits provide different levels of protec tion for the on-chip code and data, when programmed as shown in table 14. note: u : unprogrammed or ?1?, p : pr ogrammed or ?0?, x: don?t care note: security level 2 and 3 should only be programmed after flash and code verification. these security bits protect the code access through the parallel programming interface. they are set by default to level 1. though at level 2, 3 and 4, the code access thr ough the isp is still possible. default values the default value of the hsb provides parts ready to be programmed with isp ? bljb_en: bljb bit is enabled or disabled.(default : disabled) ? bljb: programmed force isp operation(default : isp inactivated)). ? lb2-0: security level four to protect the code from a parallel access with maximum security.(default : level 1) software security the software security provide two different levels of protection for the on-chip code and data, ? level 1 : no program lock features enabled. ? level 2 : isp programming and verify of the flash is disabled. program lock bit protection description security level lb0 lb1 lb2 1 u u u no program lock features enabled. 2puu movc instruction executed from external program memory is disabled from fetching code bytes from internal memory, ea is sampled and latched on reset, and further parallel programming of the flash is disabled. isp and software programming with isp are still allowed. 3xpu same as 2, also verify through parallel programming interface is disabled. 4 x x p same as 3, also external execution is disable. table 14. program lock bits
HMS99C51S/52s/54s/56s/58s 48 sep. 2004 ver 1.01 flash memory status HMS99C51S/52s/54s/56s/58s themselves are delivered in standard with the isp boot code in the flash mem- ory. after isp or parallel programming, the possible cont ents of the flash memory are summarized on figure 13. memory organization in the HMS99C51S/52s/54s/56s/58s, the lowest 4k, 8k, 16k, 24k or 32k of the 64 kb program memory ad- dress space is filled by intern al flash cells. when the ea pin is high, the processor fetches instructions from internal program flash memory. bus expansion for acces sing program memory from 4k, 8k, 16k, 24k or 32k is upward since external instruction fetches occur automatically wh en the program counter exceeds 0fffh(4k), 1fffh(8k), 3fffh(16k), 5fffh(24k) or 7fffh (32k). if the ea pin is tied low, all program memory fetches are from external memory. figure 13. flash memory possible contents virgin application application default after isp after parallel 0000 h 3fff h : hms99c54s 16kb 1fff h : hms99c52s 8kb 0fff h : HMS99C51S 4kb 5fff h : hms99c56s 24kb 7fff h : hms99c58s 32kb
HMS99C51S/52s/54s/56s/58s sep. 2004 ver 1.01 49 flash management block ? flash management block is controlled by isp command ? flash parallel mode control block flash lock control block flash rwe control block flash memory 32k decoder add reg.[2:0] data reg.[7:0] control reg.[1:0] power reg.[6:0] ebr reg.[7:0] p3.6,p3.7,p2.6,p2.7,ea ,psen ,prog reset dptr<15:0> acc<7:0> frsel[2:0] flash management block flash digital block flash analog block data_bus<7:0> hv(high voltage) generator(pumps+regulators) flash array 4k/8k/16k/24k/32kb (user area) 2kb (bootloader) 1b (hsb) x decoder x decoder y decoder & multiplexer sense amp. & io buffer
HMS99C51S/52s/54s/56s/58s 50 sep. 2004 ver 1.01 sfr register for a isp mode fcon register exists in d1 h in sfr region and defines selection of flash register operation, r/w for a flash registers, boot flash usage, selection of flas h memory space and selection of program location. fcon (flash control) register : d1 h d0 h pcon 00000000 b fcon 00000000 b ----d7 h table 15. sfr register for a flash memory bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 frsel2 frsel1 frsel0 erasesel enboot introm_en pgmsel1 pgmsel0 bit no bit mnemonic description 7~5 frsel[2:0] select register operation for flash access this bits define register operation for flash memory access see figure 16. 4 erasesel erasesel 0 : erase mode is deselected 1 : erase mode is selected 3 enboot enable boot flash cleared to disable boot rom set to map the boot rom between f800 h ~ 0ffff h . 2introm_en internal rom access enable bit 0 : external memory access over 32k bytes 1 : internal memory access to use boot rom 1~0 pgmsel[1:0] the program location select 00 : reserved 01 : 1 byte program 10 : 4 byte program 11 : 8 byte program frsel[2:0] operation 0 (000 b ) default verify / read reset contreg [7:0] data_bus [7:0] acc[7:0] 4 (100 b ) write address and data dptr[14:0] addreg[14:0] acc[7:0] datareg[7:0] 5 (101 b ) write contreg acc[7:0] contreg[7:0] 6 (110 b ) write ebr acc[7:0] ebr[6:0] 7 (111 b ) write pwr acc[7:0] pwr[7:0] table 16. register operation table for flash access
HMS99C51S/52s/54s/56s/58s sep. 2004 ver 1.01 51 bit position name function bit0 pgm_set program power setu p positive gate pump setup bit1 er_set erase power setup negat ive/positive gate pump setup bit2~bit7 - - reserved table 17. control register bit position name func tion function effect bit7 ~ bit6 veeiopt[1:0] define veei (negative pump output value) 00 : veei -09v 01 : veei -10v 10 : veei -11v bit5 ~ bit4 vppiopt[1:0] define vppi (positive gate pump output value) 00 : vppi 09v 01 : vppi 10v 10 : vppi 11v bit3 dnwopt define dnwell bias 0 : dnwell bias = v cc -v t 1 : dnwell bias = v pp -v t bit2 i_er_vfy er_vfy 1: down the level to check a erased cell (around 1v) 0: default(around 2v) bit1 i_pgm_vfy pgm_vfy 1: up the level to check a pro- grammed cell (around 6v) 0: default(around 5v) bit0 - reserved for other test table 18. power register bit position name func tion function effect bit0 ebr0 erase block (0000 h ~07ff h )erase 2k bytes bit1 ebr1 erase block (0800 h ~0fff h )erase 2k bytes bit2 ebr2 erase block (1000 h ~17ff h )erase 2k bytes bit3 ebr3 erase block (1800 h ~1fff h )erase 2k bytes bit4 ebr4 erase block (2000 h ~3fff h )erase 8k bytes bit5 ebr5 erase block (4000 h ~5fff h )erase 8k bytes bit6 ebr6 erase block (6000 h ~7fff h )erase 8k bytes table 19. erase block register(ebr)
HMS99C51S/52s/54s/56s/58s 52 sep. 2004 ver 1.01 bootloader architecture introduction the bootloader manages a communicatio n according to a specific defined pr otocol to provide the whole access and service on flash memory. furthermore, all accesses an d routines can be called fr om the user application the flash bootloader includes: ? the serial communication protocol ? the isp command decoder in order to access user flash area at a custom bootloader, user must modify the related flash registers directly. this may be necessary in case of : ? another communication interface ? different protocol (other data format, encrypted data, etc.) ? flash areas protection ? flash areas checks (crc, etc.) figure 14. diagram context description bootloader flash memory access via specific protocol access from user application
HMS99C51S/52s/54s/56s/58s sep. 2004 ver 1.01 53 bootloader functional description on the above diagram, the on-ch ip bootloader processes are: ? isp communication management the purpose of this process is to manage the communication and its protocol between the on-chip bootloader and a external device. the on-chip boot rom implement a serial protoc ol. this process translate serial commu- nication frame (uart) into flash me mory access (read, write, erase, ...) ? flash memory management this process manages low level access to flash memory (performs read, write and erase access). figure 15. bootloader functional description external host with specific protocol communication user application external host with specific protocol communication external host with specific protocol communication external host with specific protocol communication flash memory (32k bytes)
HMS99C51S/52s/54s/56s/58s 54 sep. 2004 ver 1.01 bootloader process the bootloader can be activated by hardware conditions. the hardware conditions (psen = 0, ea = 1, ale = 1) during the reset falling edge force the on-chip bootlo ader execution. this allows an application to be built that will normally execute the end user ?s code but can be manually forced into default isp operation. as psen is a an output port in normal operating mode (running user application or bootloader code) after reset, it is rec- ommended to release psen after falling edge of reset signal. the hardware conditions are sampled at reset sig- nal falling edge, thus they can be released at any tim e when reset input is low. the on-chip bootloader boot process is shown in figure 16. ? figure 16. bootloader process by hardware hardware condition= ? bljb 0 ? f bljb = 0 then reset enboot & introm_en bit(fcon) yes no no yes magnachip bootloader pc = f800 h user application pc = 0000 h bljb=0 enboot=1 bljb=1 enboot=0 (psen =0, ea =1 and ale=1) is set introm_en=0 introm_en=1
HMS99C51S/52s/54s/56s/58s sep. 2004 ver 1.01 55 in-system programming (isp) the in-system programming (isp) is performed withou t removing the microcontroller from the system. the isp facility consists of a series of internal hardware res ources coupled with internal firmware to facilitate remote programming of the HMS99C51S/52s/5 4s/56s/58s through the serial port. the magnachip microcontrollers isp facility has made in-circuit programming in an embedded application possible with a minimum of additional expense in components and circuit board area. the isp function through uart uses four pins: txd, rxd, v ss , and v cc . only a small connector needs to be available to inte rface the application to an external circuit in order to use this feature. using in-system programming (isp) the isp feature allows a wide range of baud rates in the us er application. it is also adaptable to a wide range of oscillator frequencies. this is accomplished by measurin g the bit-time of a single bit in a received character. this information is then used to program the baud rate in terms of timer counts based on the oscillator frequency. the isp feature requires that an in itial character(an uppercase u) be se nt to the HMS99C51S/52s/54s/56s/58s to establish the baud rate. the isp fi rmware provides auto-ec ho of received characters. once baud rate initial- ization has been performed, the isp firmware will only accept intel hex-type records. intel hex records consist of ascii characters used to represent hexadecimal values and are summarized below: :nnaaaarrdd...ddcc HMS99C51S/52s/54s/56s/58s will accept up to 16(10 h ) data bytes. the ?aaaa? st ring represents the address of the first byte in the record. if th ere are zero bytes in the record, this field is often set to ?0000?. the ?rr? string indicates the record type. a reco rd type of ?00? is a data record. a record type of ?01? indicates the end- of-file mark. in this application, additional record types will be added to indicate ei ther commands or data for the isp facility. the ?dd? st ring represents the data bytes. the maximum number of data bytes in a record is limited to 16(decimal). the ?cc? string represents th e checksum byte. isp commands are summarized in table 22. as a record is received by the HMS99C51S/52s/54s/56s/58s, the informa tion in the record is stored inter- nally and a checksum calculation is performed and comp ared to ?cc?. the operat ion indicated by the record type is not performed until the entire record has been received. shou ld an error occur in the checksum, the HMS99C51S/52s/54s/56s/58s will send an ?x? out the seri al port indicating a checks um error. if the check- sum calculation is found to match the ch ecksum in the record, then the comman d will be executed. in most cases, successful reception of the record will be indicated by transmitting a ?.? ch aracter out the serial port(displaying the contents of the internal program memory is an exception). in the case of a data record(record type ?00?), an additional check is made. a ?.? ch aracter will not be sent unless th e record checksum matched the calcu- lated checksum and all of the bytes in the record were successfully programmed. for a data record, an ?x? indicates that the checksum fail ed to match, and an ?r? ch aracter indicates that one of the bytes did not properly program. magnachip isp, a software utility to implement isp pr ogramming with a pc, is available from the magnachip web site. the users of this isp function should use this magnachip isp software for proper flash rom control and operation.
HMS99C51S/52s/54s/56s/58s 56 sep. 2004 ver 1.01 record type command/data function 00 program data record :nnaaaa00dd. . . . ddcc where: nn = number of bytes(hex) in record aaaa = memory address of first byte in record dd....dd=databytes cc = checksum example: :05008000af5f67f060b6 01 end of file (eof), no operation :xxxxxx01cc where: xxxxxx = required field, but value is a ?don?t care? cc = checksum example: :00000001ff 02 specify erase/write pulse :03xxxx02wweellcc where: xxxx = required field, but value is a ?don?t care? ww = write pulse ee = erase pulse high byte ll = erase pulse low byte cc = checksum example: :03000002789c40a7 03 miscellaneous write functions :nnxxxx03ffssddcc where: nn = number of bytes(hex) in record xxxx = required field, but value is a ?don?t care? 03 = write function ff = subfunction code ss = selection code dd = data input(as needed) cc = checksum subfunction code = 01(erase block) ff = 01 ss = block index in bits 6:0 (block number is designated by bit position) example: :020000030122d8 erase block 1 and 5 (position of bit 1 and 5) subfunction code = 05 (program software security bits) ff = 05 program software security bit ( level 2 inhibit reading/writing to flash) example: :0100000305f7 (program security bit) table 20. intel-hex records used by in-system programming
HMS99C51S/52s/54s/56s/58s sep. 2004 ver 1.01 57 04 display device data or blank check record type 04 causes the contents of the en tire flash array to be sent out the serial port in a formatted display. this display co nsists of an address and the contents of 16 bytes starting with that address. no display of the device contents will occur if security bit 2 has been programmed. the dumping of the device data to the serial port is terminated by the reception of any character. general format of function 04 :05xxxx04sssseeeeffcc where: 05 = number of bytes (hex) in record xxxx = required field, but value is a ?don?t care? 04 = ?display device data or blank check? function code ssss = starting address eeee = ending address ff = subfunction 00 = display data 01 = blank check cc = checksum example: :0500000440004fff0069 (display 4000 h ~ 4fff h ) 05 miscellaneous read functions general format of function 05 :02xxxx05ffsscc where: 02 = number of bytes (hex) in record xxxx = required field, but value is a ?don?t care? 05= ?miscellaneous read? function code ffss = subfunction and selection code 0001 = read copy of the signature byte - device id (family code) 0700 = read the software security bits 0703 = read the oscillation information cc = checksum example: :020000050001f0 (read copy of the signature byte - device id) record type comm and/data function table 20. intel-hex records used by in-system programming
HMS99C51S/52s/54s/56s/58s 58 sep. 2004 ver 1.01 command command name data[0] data[1] command effect 00 h program data - - program data byte bootloader will accept up to 128 data bytes. 01 h end of file - - end of file 02 h specify e/w pulse data[0] = write times low data[1] = erase times high data[2] = erase times low erase/write pulse information setup 03 h write function 01h block index bit 0 : erase blk0(0000 h ~07ff h ) ; 2k bytes bit 1 : erase blk1(0800 h ~0fff h ) ; 2k bytes bit 2 : erase blk2(1000 h ~17ff h ) ; 2k bytes bit 3 : erase blk3(1800 h ~1fff h ) ; 2k bytes bit 4 : erase blk4(2000 h ~3fff h ) ; 8k bytes bit 5 : erase blk5(4000 h ~5fff h ) ; 8k bytes bit 6 : erase blk0(6000 h ~7fff h ) ; 8k bytes bit 7 : not used 05h - program security lockbit 07h - erase user memory fully(max. 32k bytes) 04 h display function data[0:1] = start address data[2:3] = end address data[4] = 00h ( display) data[4] = 01h ( blank check) display data/blank check 05 h read function* 00 h 01 h read device id 07 h 00 h read security information 03 h read oscillator information table 21. isp commands summary
HMS99C51S/52s/54s/56s/58s sep. 2004 ver 1.01 59 serial protocol this application note describes the serial protocol us ed to program the flash code memory from magnachip microcontrollers. commands sent over the serial line are interpreted by the on-chip bootloader program. this applied for HMS99C51S/52s/54s/56s/58s. this protocol is a serial uart protocol. protocol configuration 1. physical layer the uart used to transmit information has the following configuration: ? character: 8-bit data ? parity: none ? stop: 1 bit ? flow control: none ? baudrate: autobaud is performed by the bootload er to compute the baudrate chosen by the host. 2. frame description the serial protocol is based on the intel hex-type records. intel hex records consist of ascii ch aracters used to represent hexadecima l values and are summarized below: record mark ? : ? reclen load offset record type data or info checksum 1 byte 1 byte 2 byte 1 byte n byte 1 byte uart bootloader serial protocol HMS99C51S/52s/54s/56s/58s flash host rom
HMS99C51S/52s/54s/56s/58s 60 sep. 2004 ver 1.01 ? record mark: record mark is the start of fram e. this field must contain ?:?. ? reclen: reclen specifies the number of bytes of information or data which follows the record type field of the record. ? load offset: load offset specifies the 16-bit starting load offset of th e data bytes, therefore this field is used only for data program record(see table 20). ? record type: record type specifies the command type. this field is used to interpret the remaining information within the frame. the encoding for all the current record types is described in table 20. ? data/info: data/info is a variable length field. it consists of zer o or more bytes encoded as pairs of hexadecimal digits. the meaning of data depends on the record type. ? checksum: the two?s complement of bytes that result from converting each pair of ascii hexadecimal digits to one byte of binary, and including the reclen field to and includi ng the last byte of the data/i nfo field. therefore, the sum of all the ascii pairs in a reco rd after converting to binary, from the reclen field to and including the checksum field, is zero. note: 1. a data byte is represented by two ascii characters 2. when the field load offset is not us ed, it should be coded as four ascii zero characters (?0?).
HMS99C51S/52s/54s/56s/58s sep. 2004 ver 1.01 61 protocol description 1.overview an initialization step must be performed after each reset. after microcontroller reset, the bootloader waits for an autobaud sequence. when the commun ication is initialized, the protocol depends on the record type request- ed by the host. 2.communication initialization the host initializes the communication by sending a ?u? character to he lp the bootloader to compute the baudrate (autobaud). 3.command data stream protocol all commands are sent using the same flow. initialization bootloader performs autobaud and sends back the received byte. host init communication if(not received ?u?) else communication opened u ?u? ?u? command flow bootloader gets frame, and sends back echo for each received byte host sends frame(made of 2 ascii ?:? ?:? sends first character of the frame if(not received ?:?) else sends echo and start reception characters per byte) echo analysis ...... note: all commands sent with the echo mechanism will be represented by:
HMS99C51S/52s/54s/56s/58s 62 sep. 2004 ver 1.01 3.1 write / program commands this flow is common to the following frames: ? flash programming data frame ? eof or magnachip frame (only programming magnachip frame) ? erase/write timing frame ? lockbit programming data frame a. description b. example host : 01 0010 00 55 9a bootloader : 01 0010 00 55 9a . cr lf programming data (write 55 h at address 0010 h in the flash) host : 02 0000 03 05 01 f5 bootloader : 02 0000 03 05 01 f5. cr lf programming lockbit function (write software security to level 2) send write command erase/write flow bootloader host write command ?x? & cr & lf wait write command checksum error send checksum error send security error ?p? & cr & lf no security ?.? & cr & lf wait programming wait checksum error wait security error wait command_ok command aborted command aborted command finished send command_ok y y n n
HMS99C51S/52s/54s/56s/58s sep. 2004 ver 1.01 63 3.2 blank check command a. description b. example host : 05 0000 04 0000 7fff 01 78 bootloader : 05 0000 04 0000 7fff 01 78 . cr lf blank check ok bootloader : 05 0000 04 0000 7fff 01 70 x cr lf cr lf blank check with checksum error host : 05 0000 04 0000 7fff 01 70 bootloader : 05 0000 04 0000 7fff 01 78 xxxx cr lf blank check failure at address xxxx send first address send blank check command blank check flow bootloader host blank check command ?x? & cr & lf wait blank check command checksum error send checksum error send command_ok ?.? & cr & lf flash blank ?address? & cr & lf wait checksum error wait command_ok wait address not erased command aborted command aborted command finished not erased or or y n y n
HMS99C51S/52s/54s/56s/58s 64 sep. 2004 ver 1.01 3.3 display data a. description b. example host : 05 0000 04 0000 0020 00 d7 bootloader : 05 0000 04 0000 0020 00 d7 bootloader 0000=-----data------ / cr lf (16 data) bootloader 0010=-----data------ / cr lf (16 data) bootloader 0020=data cr lf ( 1 data) display data from address 0000 h to 0020 h send display command display flow bootloader host display command ?x? & cr & lf wait display command checksum error send checksum error send security error ?.? & cr & lf rd_wr_security ?address=? wait checksum error wait security error command aborted command aborted command finished or or read data all data read send display data complete frame out ?reading value? ?/? & cr & lf wait display data all data read note: the maximum size of display bl ock is equal to the flash rom size. n y y n y n y n
HMS99C51S/52s/54s/56s/58s sep. 2004 ver 1.01 65 3.4. read function this flow is similar fo r the following frames: ? reading frame ? eof frame/ magnachip frame (only reading magnachip frame) a. description b. example host : 02 0000 05 00 01 f8 bootloader : 02 0000 05 00 01 f8 value . cr lf read function (read device id) send data read send read command read flow bootloader host read command ?x? & cr & lf wait read command checksum error send checksum error send security error ?l? & cr & lf rd_wr_security ?value? & cr & lf wait checksum error wait security error wait value of data command aborted command aborted command finished or or read value y n y n
HMS99C51S/52s/54s/56s/58s 66 sep. 2004 ver 1.01 isp method for pc(magnachip winisp) getting started / installation the following section details the procedure for accomplishing the inst allation procedure. 1. connect the serial(rs-232c) cable between a target board and the com1 serial port of your pc. 2. configure the com1 serial port of your pc as following. ? baudrate : 115,200 ? data bit : 8 ? parity : no ? stop bit : 1 ? flow control : no 3. turn your target b/d power switch on. your target b/d must be configured to enter the isp mode. 4. run the magnachip isp software. 5. press the reset button in the isp s/w. if the status windows shows a message as "conn ected", all the conditions for isp are provided. if you press the reset button again after connected, the status windows will show the message as "disconnect- ed". please discard it because the HMS99C51S/52s/54s/5 6s/58s can not check the reset button after connected successfully.
HMS99C51S/52s/54s/56s/58s sep. 2004 ver 1.01 67 basic information function description load hex file load the data from the selected file storage into the memory buffer. save hex file save the current data in your memo ry buffer to a disk storage by using the intel hex format. erase erase the data in your target mcu before programming it. blank check verify whether or not a device is in an erased or unprogrammed state. program this button enables you to place new data from the memory buffer into the target device. read read the data in the target mcu into the buffer for examination. the checksum will be displa yed on the checksum box. verify assures that da ta in the device matches data in the memory buffer. if your device is secured, a verification error is detected. lock secures devices so that their content can no longer be examined or modified. table 22. isp function description
HMS99C51S/52s/54s/56s/58s 68 sep. 2004 ver 1.01 erase option select blocks for erasure. auto blank check & program & verify auto lock if selected with check mark, the security locking is performed after erasure. connect connect a mcu in your target board with displaying as ?connected? in the status box. users have to press this butt on at least one time to initialize a target mcu for entering the isp mode. if failed to enter the isp mode, all the buttons are unavailable. and, after entering su ccessfully, the connect button will be unavailable. edit buffer modify the data in the sele cted address in your buffer memory fill buffer fill the selected area with a data. goto display the selected page. osc. ______ mhz display your target system?s oscillator value with discarding below point. start ______ starting address end ______ end address checksum=8000 display the c hecksum(hexdecimal) after re ading the target device. com port select serial port. baud rate select uart baud rate. select device sele ct target device. page up key display the previous page of your memory buffer. page down key display the higher page than the current location. function description table 22. isp function description
HMS99C51S/52s/54s/56s/58s sep. 2004 ver 1.01 69 hardware conditions to enter the isp mode the in-system programming (isp) is performed without removing the microcontroller from the system. the in- system programming(isp) facility consists of a series of internal hardware resources coupled with internal firm- ware through the serial port. the in-system programming (isp) facility make in-circuit programming in an em- bedded application possible with a minimum of additional expense in components and circuit board area. the bootloader can be executed by holding psen low, ea/ v pp greater than v ih (such as +5v), and ale/ prog high at the falling edge of reset. the isp function block uses four pins: txd, rxd, v ss , and v cc . only a small connector needs to be ava ilable to interface your appl ication to an external circuit in order to use this feature. ea / v pp ale / prog psen v cc reset rxd / p3.0 txd / p3.1 xtal2 xtal1 v ss v cc (+5v) v cc (+5v) : 1 v cc (+5v) : 1 v ss (0v) : 0 isp configuration hms99c58s

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